Clock signals are commonly used in integrated circuits. Dual clocks or dual clock domains can result in un-synchronizations and meta-unstability. Clocks in two different chips can be skewed by various factors including, for example, packaging, routing, connections, etc., that can be part of and/or worsen un-synchronization. To minimize data loss and meta-unstability of clock un-synchronization, some approaches use both the rising and falling edges of a clock for triggering, and switch between these triggering edges as appropriate. Those approaches, however, require a control pin for such switching, which needs to be calibrated from time to time, and is therefore undesirable.
Like reference symbols in the various drawings indicate like elements.